AO4468 30v n-channel mosfet general description product summary v ds i d (at v gs =10v) 10.5a r ds(on) (at v gs =10v) < 17m w r ds(on) (at v gs = 4.5v) < 23m w esd protected 100% uis tested 100% r g tested symbol v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r q jl c thermal characteristics w 3.1 2 t a =70c junction and storage temperature range -55 to 150 units parameter typ max c/w r q ja 31 59 40 maximum junction-to-ambient a v 20 gate-source voltage mj avalanche current c 18 a 19 a the AO4468 combines advanced trench mosfet technology with a low resistance package to provide extremely low r ds(on) . this device is ideal for load switch and battery protection applications. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted 30v 10.5 8.5 50 drain-source voltage 30 t a =25c t a =70c power dissipation b p d avalanche energy l=0.1mh c pulsed drain current c continuous drain current t a =25c i d maximum junction-to-lead c/w c/w maximum junction-to-ambient a d 16 75 24 soic-8 top view bottom view d d d d s s s g g ds rev 6: december 2010 www.aosmd.com page 1 of 5
AO4468 symbol min typ max units bv dss 30 v v ds =30v, v gs =0v 1 t j =55c 5 i gss 10 m a v gs(th) gate threshold voltage 1.2 1.8 2.4 v i d(on) 50 a 14 17 t j =125c 20 24 18 23 m w g fs 36 s v sd 0.75 1 v i s 4 a c iss 740 888 pf c oss 110 145 pf c rss 82 115 pf r g 0.5 1.1 1.7 w q g (10v) 15 nc q g (4.5v) 7.5 nc q gs 2.5 nc q gd 3 nc t d(on) 5 ns t r 3.5 ns t d(off) 19 ns t f 3.5 ns t rr 18 22 ns q rr 9 12 nc this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. i f =10.5a, di/dt=100a/ m s maximum body-diode continuous current input capacitance output capacitance turn-on delaytime dynamic parameters turn-on rise time turn-off delaytime v gs =10v, v ds =15v, r l =1.45 w , r gen =3 w gate source charge gate drain charge total gate charge body diode reverse recovery charge m w on state drain current i s =1a,v gs =0v v ds =5v, i d =10.5a v gs =4.5v, i d =9a forward transconductance diode forward voltage m a v ds =v gs i d =250 m a v ds =0v, v gs =16v zero gate voltage drain current gate-body leakage current i d =250 m a, v gs =0v v gs =10v, v ds =5v v gs =10v, i d =10.5a r ds(on) static drain-source on-resistance i dss drain-source breakdown voltage reverse transfer capacitance i f =10.5a, di/dt=100a/ m s v gs =0v, v ds =15v, f=1mhz switching parameters body diode reverse recovery time gate resistance v gs =0v, v ds =0v, f=1mhz turn-off fall time total gate charge v gs =10v, v ds =15v, i d =10.5a electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the value in any given application depends on the user' s specific board design. b. the power dissipation p d is based on t j(max) =150c, using 10s junction-to-ambient thermal resistance. c. repetitive rating, pulse width limited by junct ion temperature t j(max) =150c. ratings are based on low frequency and duty cycles to keep initialt j =25c. d. the r q ja is the sum of the thermal impedence from junction to lead r q jl and lead to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-ambien t thermal impedence which is measured with the devi ce mounted on 1in 2 fr-4 board with 2oz. copper, assuming a maximum junction temperatur e of t j(max) =150c. the soa curve provides a single pulse ratin g. rev 6: december 2010 www.aosmd.com page 2 of 5
AO4468 typical electrical and thermal characteristics 17 52 10 0 18 40 0 5 10 15 20 25 30 1 2 3 4 5 v gs (volts) figure 2: transfer characteristics (note e) i d (a) 10 15 20 25 0 5 10 15 20 i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) r ds(on) (m w ww w ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 v sd (volts) figure 6: body-diode characteristics (note e) i s (a) 25c 125c 0.8 1 1.2 1.4 1.6 1.8 0 25 50 75 100 125 150 175 200 temperature (c) figure 4: on-resistance vs. junction temperature (note e) normalized on-resistance v gs =4.5v i d =9a v gs =10v i d =10.5a 10 15 20 25 30 35 40 2 4 6 8 10 v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) r ds(on) (m w ww w ) 25c 125c v ds =5v v gs =4.5v v gs =10v i d =10.5a 25c 125c 0 5 10 15 20 25 30 0 1 2 3 4 5 v ds (volts) fig 1: on-region characteristics (note e) i d (a) v gs =2.5v 3v 4v 10v 3.5v rev 6: december 2010 www.aosmd.com page 3 of 5
AO4468 typical electrical and thermal characteristics 0 2 4 6 8 10 0 5 10 15 q g (nc) figure 7: gate-charge characteristics v gs (volts) 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss c oss c rss v ds =15v i d =10.5a 1 10 100 1000 10000 0.00001 0.001 0.1 10 1000 pulse width (s) figure 11: single pulse power rating junction-to- ambient (note f) power (w) t a =25c 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 v ds (volts) i d (amps) figure 10: maximum forward biased safe operating area (note f) 10 m s 10s 1ms dc r ds(on) limited t j(max) =150c t a =25c 100 m s 10ms 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 12: normalized maximum transient thermal imp edance (note f) z q qq q ja normalized transient thermal resistance d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse r q ja =75c/w single pulse rev 6: december 2010 www.aosmd.com page 4 of 5
AO4468 - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i unclamped inductive switching (uis) test circuit & waveforms ig vgs - + vdc dut l vds vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar dss 2 e = 1/2 li di/dt i rm rr vdd vdd q = - idt ar ar t rr rev 6: december 2010 www.aosmd.com page 5 of 5
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